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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:48 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:48 -0400 |
| commit | b8631d9ae8a1f9c478ad81c7cc23304b4a7ca919 (patch) | |
| tree | 802f928c1e7a04b7ad9288d037ee455b595a7aef /src/doc | |
| parent | c735ef6cb08f109a614383e12f9f55148bcf0257 (diff) | |
| download | gem5-b8631d9ae8a1f9c478ad81c7cc23304b4a7ca919.tar.xz | |
mem: Add tWR to DRAM activate and precharge constraints
This patch adds the write recovery time to the DRAM timing
constraints, and changes the current tRASDoneAt to a more generic
preAllowedAt, capturing when a precharge is allowed to take place.
The part of the DRAM access code that accounts for the precharge and
activate constraints is updated accordingly.
Diffstat (limited to 'src/doc')
0 files changed, 0 insertions, 0 deletions