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author | Gabe Black <gabeblack@google.com> | 2020-01-09 00:53:15 -0800 |
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committer | Gabe Black <gabeblack@google.com> | 2020-01-14 02:19:19 +0000 |
commit | 2012a0c6519a7198e7158f9bc07b97b98fdd357a (patch) | |
tree | 6303430fab5b0994bc2d2a27d835e8233067beba /src/doxygen | |
parent | 7085b8561478fcb416fc1eaaaeb778f89dd4d3c2 (diff) | |
download | gem5-2012a0c6519a7198e7158f9bc07b97b98fdd357a.tar.xz |
x86: Move miscreg initialization to the ISA class.
The initCPU function was setting a lot of values to zero or other
initial values, but that's something the ISA object can do as part of
its clear() method. This gets rid of a lot of code that was
individually zeroing registers, and also centralizes responsibility
for those registers in the ISA.
Change-Id: Iafcffd3f9329c39f77009b38b1696f91c36c117e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24185
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/doxygen')
0 files changed, 0 insertions, 0 deletions