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| author | Ani Udipi <ani.udipi@arm.com> | 2013-11-01 11:56:17 -0400 |
|---|---|---|
| committer | Ani Udipi <ani.udipi@arm.com> | 2013-11-01 11:56:17 -0400 |
| commit | be62a142cf0513bfa69f4837565889dcb447fae0 (patch) | |
| tree | 90e63c989d8db5a18be46ca426918fd0696154e0 /src/doxygen | |
| parent | d4cf009b95d34b75408363bc085c2e9e9de458d9 (diff) | |
| download | gem5-be62a142cf0513bfa69f4837565889dcb447fae0.tar.xz | |
mem: Schedule time for DRAM event taking tRAS into account
This patch changes the time the controller is woken up to take the
next scheduling decisions. tRAS is now handled in estimateLatency and
doDRAMAccess and we do not need to worry about it at scheduling
time. The earliest we need to wake up is to do a pre-charge, row
access and column access before the bus becomes free for use.
Diffstat (limited to 'src/doxygen')
0 files changed, 0 insertions, 0 deletions