gpu-compute, hsail: pass GPUDynInstPtr to getRegisterIndex()

for HSAIL an operand's indices into the register files may be calculated
trivially, because the operands are always read from a register file, or are
an immediate.

for machine ISA, however, an op selector may specify special registers, or
may specify special SGPRs with an alias op selector value. the location of
some of the special registers values are dependent on the size of the RF
in some cases. here we add a way for the underlying getRegisterIndex()
method to know about the size of the RFs, so that it may find the relative
positions of the special register values.

1 files changed, 3 insertions, 3 deletions

diff --git a/src/gpu-compute/condition_register_state.cc b/src/gpu-compute/condition_register_state.cc
index f3f2d2927..08555bb7c 100644
--- a/src/gpu-compute/condition_register_state.cc
+++ b/src/gpu-compute/condition_register_state.cc
@@ -62,19 +62,19 @@ ConditionRegisterState::init(uint32_t _size)
 }
 
 void
-ConditionRegisterState::exec(GPUStaticInst *ii, Wavefront *w)
+ConditionRegisterState::exec(GPUDynInstPtr ii, Wavefront *w)
 {
     // iterate over all operands
     for (auto i = 0; i < ii->getNumOperands(); ++i) {
         // is this a condition register destination operand?
         if (ii->isCondRegister(i) && ii->isDstOperand(i)) {
             // mark the register as busy
-            markReg(ii->getRegisterIndex(i), 1);
+            markReg(ii->getRegisterIndex(i, ii), 1);
             uint32_t pipeLen =  w->computeUnit->spBypassLength();
 
             // schedule an event for marking the register as ready
             w->computeUnit->
-                registerEvent(w->simdId, ii->getRegisterIndex(i),
+                registerEvent(w->simdId, ii->getRegisterIndex(i, ii),
                               ii->getOperandSize(i),
                               w->computeUnit->shader->tick_cnt +
                               w->computeUnit->shader->ticks(pipeLen), 0);