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authorTony Gutierrez <anthony.gutierrez@amd.com>2016-10-26 22:47:43 -0400
committerTony Gutierrez <anthony.gutierrez@amd.com>2016-10-26 22:47:43 -0400
commit844fb845a51b15f13c7c744e0d5fdf5567c3da98 (patch)
tree407cd19c909cdf3cd4da7947ad86dfbd4470ef68 /src/gpu-compute/fetch_unit.cc
parentd327cdba078e0956596513b518731e9ec730723f (diff)
downloadgem5-844fb845a51b15f13c7c744e0d5fdf5567c3da98.tar.xz
gpu-compute, hsail: make the PC a byte address, not an instruction index
currently the PC is incremented on an instruction granularity, and not as an instruction's byte address. machine ISA instructions assume the PC is a byte address, and is incremented accordingly. here we make the GPU model, and the HSAIL instructions treat the PC as a byte address as well.
Diffstat (limited to 'src/gpu-compute/fetch_unit.cc')
-rw-r--r--src/gpu-compute/fetch_unit.cc5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/gpu-compute/fetch_unit.cc b/src/gpu-compute/fetch_unit.cc
index 2ea7f1f9d..1b19a3223 100644
--- a/src/gpu-compute/fetch_unit.cc
+++ b/src/gpu-compute/fetch_unit.cc
@@ -122,11 +122,10 @@ FetchUnit::initiateFetch(Wavefront *wavefront)
* instrutions on a 32b granularity so we must account for that here.
*/
for (int i = 0; i < wavefront->instructionBuffer.size(); ++i) {
- int current_inst_size =
+ vaddr +=
wavefront->instructionBuffer.at(i)->staticInstruction()->instSize();
- vaddr += current_inst_size / sizeof(uint32_t);
}
- vaddr = wavefront->basePtr + vaddr * sizeof(GPUStaticInst*);
+ vaddr = wavefront->basePtr + vaddr;
DPRINTF(GPUTLB, "CU%d: WF[%d][%d]: Initiating fetch translation: %#x\n",
computeUnit->cu_id, wavefront->simdId, wavefront->wfSlotId, vaddr);