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author | Tony Gutierrez <anthony.gutierrez@amd.com> | 2016-10-26 22:47:49 -0400 |
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committer | Tony Gutierrez <anthony.gutierrez@amd.com> | 2016-10-26 22:47:49 -0400 |
commit | b63eb1302b006682bd227a5e236f7b3b95e9b8e8 (patch) | |
tree | 87d8422e6bbc7cd88e33d9408e2010c2bdd3c337 /src/gpu-compute/gpu_dyn_inst.hh | |
parent | aa7364276f16bbe6aa300b43bc57ff1b73be42a7 (diff) | |
download | gem5-b63eb1302b006682bd227a5e236f7b3b95e9b8e8.tar.xz |
gpu-compute, hsail: pass GPUDynInstPtr to getRegisterIndex()
for HSAIL an operand's indices into the register files may be calculated
trivially, because the operands are always read from a register file, or are
an immediate.
for machine ISA, however, an op selector may specify special registers, or
may specify special SGPRs with an alias op selector value. the location of
some of the special registers values are dependent on the size of the RF
in some cases. here we add a way for the underlying getRegisterIndex()
method to know about the size of the RFs, so that it may find the relative
positions of the special register values.
Diffstat (limited to 'src/gpu-compute/gpu_dyn_inst.hh')
-rw-r--r-- | src/gpu-compute/gpu_dyn_inst.hh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/gpu-compute/gpu_dyn_inst.hh b/src/gpu-compute/gpu_dyn_inst.hh index 527b87b4c..c30871f5e 100644 --- a/src/gpu-compute/gpu_dyn_inst.hh +++ b/src/gpu-compute/gpu_dyn_inst.hh @@ -194,7 +194,8 @@ class GPUDynInst : public GPUExecContext int getNumOperands(); bool isVectorRegister(int operandIdx); bool isScalarRegister(int operandIdx); - int getRegisterIndex(int operandIdx); + bool isCondRegister(int operandIdx); + int getRegisterIndex(int operandIdx, GPUDynInstPtr gpuDynInst); int getOperandSize(int operandIdx); bool isDstOperand(int operandIdx); bool isSrcOperand(int operandIdx); |