summaryrefslogtreecommitdiff
path: root/src/gpu-compute/gpu_static_inst.hh
diff options
context:
space:
mode:
authorTony Gutierrez <anthony.gutierrez@amd.com>2016-10-26 22:47:49 -0400
committerTony Gutierrez <anthony.gutierrez@amd.com>2016-10-26 22:47:49 -0400
commitb63eb1302b006682bd227a5e236f7b3b95e9b8e8 (patch)
tree87d8422e6bbc7cd88e33d9408e2010c2bdd3c337 /src/gpu-compute/gpu_static_inst.hh
parentaa7364276f16bbe6aa300b43bc57ff1b73be42a7 (diff)
downloadgem5-b63eb1302b006682bd227a5e236f7b3b95e9b8e8.tar.xz
gpu-compute, hsail: pass GPUDynInstPtr to getRegisterIndex()
for HSAIL an operand's indices into the register files may be calculated trivially, because the operands are always read from a register file, or are an immediate. for machine ISA, however, an op selector may specify special registers, or may specify special SGPRs with an alias op selector value. the location of some of the special registers values are dependent on the size of the RF in some cases. here we add a way for the underlying getRegisterIndex() method to know about the size of the RFs, so that it may find the relative positions of the special register values.
Diffstat (limited to 'src/gpu-compute/gpu_static_inst.hh')
-rw-r--r--src/gpu-compute/gpu_static_inst.hh13
1 files changed, 11 insertions, 2 deletions
diff --git a/src/gpu-compute/gpu_static_inst.hh b/src/gpu-compute/gpu_static_inst.hh
index 2fa1e0ca5..e851c52e6 100644
--- a/src/gpu-compute/gpu_static_inst.hh
+++ b/src/gpu-compute/gpu_static_inst.hh
@@ -83,7 +83,10 @@ class GPUStaticInst : public GPUStaticInstFlags
virtual bool isSrcOperand(int operandIndex) = 0;
virtual bool isDstOperand(int operandIndex) = 0;
virtual int getOperandSize(int operandIndex) = 0;
- virtual int getRegisterIndex(int operandIndex) = 0;
+
+ virtual int getRegisterIndex(int operandIndex,
+ GPUDynInstPtr gpuDynInst) = 0;
+
virtual int numDstRegOperands() = 0;
virtual int numSrcRegOperands() = 0;
@@ -286,7 +289,13 @@ class KernelLaunchStaticInst : public GPUStaticInst
bool isSrcOperand(int operandIndex) { return false; }
bool isDstOperand(int operandIndex) { return false; }
int getOperandSize(int operandIndex) { return 0; }
- int getRegisterIndex(int operandIndex) { return 0; }
+
+ int
+ getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
+ {
+ return 0;
+ }
+
int numDstRegOperands() { return 0; }
int numSrcRegOperands() { return 0; }
bool isValid() const { return true; }