arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.

Neither assert(0) nor assert(false) give any hint as to why control
getting to them is bad, and their more descriptive versions,
assert(0 && "description") and assert(false && "description"), jury
rig assert to add an error message when the utility function panic()
already does that directly with better formatting options.

This change replaces that flavor of call to assert with panic, except
in the actual code which processes the formatting that panic uses (to
avoid infinitely recurring error handling), and in some *.sm files
since I don't know what rules those have to follow and don't want to
accidentaly break them.

Change-Id: I8addfbfaf77eaed94ec8191f2ae4efb477cefdd0
Reviewed-on: https://gem5-review.googlesource.com/c/14636
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

1 files changed, 11 insertions, 10 deletions

diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc
index fea6183ed..dbf7d2628 100644
--- a/src/gpu-compute/gpu_tlb.cc
+++ b/src/gpu-compute/gpu_tlb.cc
@@ -45,6 +45,7 @@
 #include "arch/x86/regs/misc.hh"
 #include "arch/x86/x86_traits.hh"
 #include "base/bitfield.hh"
+#include "base/logging.hh"
 #include "base/output.hh"
 #include "base/trace.hh"
 #include "cpu/base.hh"
@@ -1150,16 +1151,16 @@ namespace X86ISA
 
         if ((inUser && !tlb_entry->user) ||
             (mode == BaseTLB::Write && badWrite)) {
-           // The page must have been present to get into the TLB in
-           // the first place. We'll assume the reserved bits are
-           // fine even though we're not checking them.
-           assert(false);
+            // The page must have been present to get into the TLB in
+            // the first place. We'll assume the reserved bits are
+            // fine even though we're not checking them.
+            panic("Page fault detected");
         }
 
         if (storeCheck && badWrite) {
-           // This would fault if this were a write, so return a page
-           // fault that reflects that happening.
-           assert(false);
+            // This would fault if this were a write, so return a page
+            // fault that reflects that happening.
+            panic("Page fault detected");
         }
     }
 
@@ -1362,7 +1363,7 @@ namespace X86ISA
              */
             handleTranslationReturn(virtPageAddr, TLB_MISS, pkt);
         } else {
-            assert(false);
+            panic("Unexpected TLB outcome %d", outcome);
         }
     }
 
@@ -1607,7 +1608,7 @@ namespace X86ISA
     {
         // The CPUSidePort never sends anything but replies. No retries
         // expected.
-        assert(false);
+        panic("recvReqRetry called");
     }
 
     AddrRangeList
@@ -1648,7 +1649,7 @@ namespace X86ISA
     {
         // No retries should reach the TLB. The retries
         // should only reach the TLBCoalescer.
-        assert(false);
+        panic("recvReqRetry called");
     }
 
     void