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authorGabe Black <gabeblack@google.com>2018-01-05 15:01:00 -0800
committerGabe Black <gabeblack@google.com>2018-01-20 08:06:56 +0000
commit2a15bfd79ced20a6d4cbf0a0a4c2fbb1444b9a44 (patch)
treed1fec5a31a00928dc9d5a3f4f05394236187d19c /src/gpu-compute/gpu_tlb.cc
parentb1ade08b2da4a0b398b69ea4eb2de35b08941826 (diff)
downloadgem5-2a15bfd79ced20a6d4cbf0a0a4c2fbb1444b9a44.tar.xz
arch, mem: Make the page table lookup function return a pointer.
This avoids having a copy in the lookup function itself, and the declaration of a lot of temporary TLB entry pointers in callers. The gpu TLB seems to have had the most dependence on the original signature of the lookup function, partially because it was relying on a somewhat unsafe copy to a TLB entry using a base class pointer type. Change-Id: I8b1cf494468163deee000002d243541657faf57f Reviewed-on: https://gem5-review.googlesource.com/7343 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/gpu-compute/gpu_tlb.cc')
-rw-r--r--src/gpu-compute/gpu_tlb.cc72
1 files changed, 36 insertions, 36 deletions
diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc
index b5411f82c..9cbf3e8fa 100644
--- a/src/gpu-compute/gpu_tlb.cc
+++ b/src/gpu-compute/gpu_tlb.cc
@@ -808,31 +808,31 @@ namespace X86ISA
"at pc %#x.\n", vaddr, tc->instAddr());
Process *p = tc->getProcessPtr();
- GpuTlbEntry newEntry;
- bool success = p->pTable->lookup(vaddr, newEntry);
+ TlbEntry *newEntry = p->pTable->lookup(vaddr);
- if (!success && mode != BaseTLB::Execute) {
+ if (!newEntry && mode != BaseTLB::Execute) {
// penalize a "page fault" more
- if (timing) {
+ if (timing)
latency += missLatency2;
- }
if (p->fixupStackFault(vaddr))
- success = p->pTable->lookup(vaddr, newEntry);
+ newEntry = p->pTable->lookup(vaddr);
}
- if (!success) {
+ if (!newEntry) {
return std::make_shared<PageFault>(vaddr, true,
mode, true,
false);
} else {
- newEntry.valid = success;
Addr alignedVaddr = p->pTable->pageAlign(vaddr);
DPRINTF(GPUTLB, "Mapping %#x to %#x\n",
- alignedVaddr, newEntry.pageStart());
+ alignedVaddr, newEntry->pageStart());
- entry = insert(alignedVaddr, newEntry);
+ GpuTlbEntry gpuEntry;
+ *(TlbEntry *)&gpuEntry = *newEntry;
+ gpuEntry.valid = true;
+ entry = insert(alignedVaddr, gpuEntry);
}
DPRINTF(GPUTLB, "Miss was serviced.\n");
@@ -1330,25 +1330,27 @@ namespace X86ISA
safe_cast<TranslationState*>(pkt->senderState);
Process *p = sender_state->tc->getProcessPtr();
- TlbEntry newEntry;
Addr vaddr = pkt->req->getVaddr();
#ifndef NDEBUG
Addr alignedVaddr = p->pTable->pageAlign(vaddr);
assert(alignedVaddr == virtPageAddr);
#endif
- bool success;
- success = p->pTable->lookup(vaddr, newEntry);
- if (!success && sender_state->tlbMode != BaseTLB::Execute) {
- if (p->fixupStackFault(vaddr)) {
- success = p->pTable->lookup(vaddr, newEntry);
- }
+ TlbEntry *newEntry = p->pTable->lookup(vaddr);
+ if (!newEntry && sender_state->tlbMode != BaseTLB::Execute &&
+ p->fixupStackFault(vaddr)) {
+ newEntry = p->pTable->lookup(vaddr);
}
- DPRINTF(GPUTLB, "Mapping %#x to %#x\n", alignedVaddr,
- newEntry.pageStart());
+ if (newEntry) {
+ DPRINTF(GPUTLB, "Mapping %#x to %#x\n", alignedVaddr,
+ newEntry->pageStart());
- sender_state->tlbEntry =
- new GpuTlbEntry(0, newEntry.vaddr, newEntry.paddr, success);
+ sender_state->tlbEntry =
+ new GpuTlbEntry(0, newEntry->vaddr, newEntry->paddr, true);
+ } else {
+ sender_state->tlbEntry =
+ new GpuTlbEntry(0, 0, 0, false);
+ }
handleTranslationReturn(virtPageAddr, TLB_MISS, pkt);
} else if (outcome == MISS_RETURN) {
@@ -1524,7 +1526,6 @@ namespace X86ISA
virt_page_addr);
Process *p = tc->getProcessPtr();
- TlbEntry newEntry;
Addr vaddr = pkt->req->getVaddr();
#ifndef NDEBUG
@@ -1532,10 +1533,10 @@ namespace X86ISA
assert(alignedVaddr == virt_page_addr);
#endif
- bool success = p->pTable->lookup(vaddr, newEntry);
- if (!success && sender_state->tlbMode != BaseTLB::Execute) {
- if (p->fixupStackFault(vaddr))
- success = p->pTable->lookup(vaddr, newEntry);
+ TlbEntry *newEntry = p->pTable->lookup(vaddr);
+ if (!newEntry && sender_state->tlbMode != BaseTLB::Execute &&
+ p->fixupStackFault(vaddr)) {
+ newEntry = p->pTable->lookup(vaddr);
}
if (!sender_state->prefetch) {
@@ -1544,24 +1545,23 @@ namespace X86ISA
assert(success);
DPRINTF(GPUTLB, "Mapping %#x to %#x\n", alignedVaddr,
- newEntry.pageStart());
+ newEntry->pageStart());
- sender_state->tlbEntry = new GpuTlbEntry(0, newEntry.vaddr,
- newEntry.paddr,
- success);
+ sender_state->tlbEntry =
+ new GpuTlbEntry(0, newEntry->vaddr,
+ newEntry->paddr, success);
} else {
// If this was a prefetch, then do the normal thing if it
// was a successful translation. Otherwise, send an empty
// TLB entry back so that it can be figured out as empty and
// handled accordingly.
- if (success) {
+ if (newEntry) {
DPRINTF(GPUTLB, "Mapping %#x to %#x\n", alignedVaddr,
- newEntry.pageStart());
+ newEntry->pageStart());
- sender_state->tlbEntry = new GpuTlbEntry(0,
- newEntry.vaddr,
- newEntry.paddr,
- success);
+ sender_state->tlbEntry =
+ new GpuTlbEntry(0, newEntry->vaddr,
+ newEntry->paddr, success);
} else {
DPRINTF(GPUPrefetch, "Prefetch failed %#x\n",
alignedVaddr);