misc: Using smart pointers for memory Requests

This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.

Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

1 files changed, 9 insertions, 8 deletions

diff --git a/src/gpu-compute/gpu_tlb.hh b/src/gpu-compute/gpu_tlb.hh
index f479eb6ce..04d9bfce8 100644
--- a/src/gpu-compute/gpu_tlb.hh
+++ b/src/gpu-compute/gpu_tlb.hh
@@ -113,8 +113,8 @@ namespace X86ISA
              * may be responsible for cleaning itslef up which will happen in
              * this function. Once it's called the object is no longer valid.
              */
-            virtual void finish(Fault fault, RequestPtr req, ThreadContext *tc,
-                    Mode mode) = 0;
+            virtual void finish(Fault fault, const RequestPtr &req,
+                                ThreadContext *tc, Mode mode) = 0;
         };
 
         void dumpAll();
@@ -177,9 +177,9 @@ namespace X86ISA
          */
         std::vector<EntryList> entryList;
 
-        Fault translateInt(RequestPtr req, ThreadContext *tc);
+        Fault translateInt(const RequestPtr &req, ThreadContext *tc);
 
-        Fault translate(RequestPtr req, ThreadContext *tc,
+        Fault translate(const RequestPtr &req, ThreadContext *tc,
                 Translation *translation, Mode mode, bool &delayedResponse,
                 bool timing, int &latency);
 
@@ -222,10 +222,10 @@ namespace X86ISA
         void printAccessPattern();
 
 
-        Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode,
-                              int &latency);
+        Fault translateAtomic(const RequestPtr &req, ThreadContext *tc,
+                              Mode mode, int &latency);
 
-        void translateTiming(RequestPtr req, ThreadContext *tc,
+        void translateTiming(const RequestPtr &req, ThreadContext *tc,
                              Translation *translation, Mode mode,
                              int &latency);
 
@@ -239,7 +239,8 @@ namespace X86ISA
         virtual void unserialize(CheckpointIn& cp);
         void issueTranslation();
         enum tlbOutcome {TLB_HIT, TLB_MISS, PAGE_WALK, MISS_RETURN};
-        bool tlbLookup(RequestPtr req, ThreadContext *tc, bool update_stats);
+        bool tlbLookup(const RequestPtr &req,
+                       ThreadContext *tc, bool update_stats);
 
         void handleTranslationReturn(Addr addr, tlbOutcome outcome,
                                      PacketPtr pkt);