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authorGabe Black <gabeblack@google.com>2019-03-07 03:02:35 -0800
committerGabe Black <gabeblack@google.com>2019-03-19 10:22:50 +0000
commitd3d24835bcc03ecf312ac6ba7df114656770730f (patch)
tree43bb564a7bc3e22ffd7b1b906f6f96742ecb619a /src/gpu-compute/tlb_coalescer.cc
parent378d9ccbeb4053aeeab002159b26625854af54f7 (diff)
downloadgem5-d3d24835bcc03ecf312ac6ba7df114656770730f.tar.xz
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
Replace the getMasterPort, getSlavePort, and getEthPort functions with getPort, and remove extraneous mechanisms that are no longer necessary. Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/gpu-compute/tlb_coalescer.cc')
-rw-r--r--src/gpu-compute/tlb_coalescer.cc20
1 files changed, 6 insertions, 14 deletions
diff --git a/src/gpu-compute/tlb_coalescer.cc b/src/gpu-compute/tlb_coalescer.cc
index 193c44ed8..3b7631a74 100644
--- a/src/gpu-compute/tlb_coalescer.cc
+++ b/src/gpu-compute/tlb_coalescer.cc
@@ -67,31 +67,23 @@ TLBCoalescer::TLBCoalescer(const Params *p)
}
}
-BaseSlavePort&
-TLBCoalescer::getSlavePort(const std::string &if_name, PortID idx)
+Port &
+TLBCoalescer::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "slave") {
if (idx >= static_cast<PortID>(cpuSidePort.size())) {
- panic("TLBCoalescer::getSlavePort: unknown index %d\n", idx);
+ panic("TLBCoalescer::getPort: unknown index %d\n", idx);
}
return *cpuSidePort[idx];
- } else {
- panic("TLBCoalescer::getSlavePort: unknown port %s\n", if_name);
- }
-}
-
-BaseMasterPort&
-TLBCoalescer::getMasterPort(const std::string &if_name, PortID idx)
-{
- if (if_name == "master") {
+ } else if (if_name == "master") {
if (idx >= static_cast<PortID>(memSidePort.size())) {
- panic("TLBCoalescer::getMasterPort: unknown index %d\n", idx);
+ panic("TLBCoalescer::getPort: unknown index %d\n", idx);
}
return *memSidePort[idx];
} else {
- panic("TLBCoalescer::getMasterPort: unknown port %s\n", if_name);
+ panic("TLBCoalescer::getPort: unknown port %s\n", if_name);
}
}