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| author | Tony Gutierrez <anthony.gutierrez@amd.com> | 2016-10-26 22:47:49 -0400 |
|---|---|---|
| committer | Tony Gutierrez <anthony.gutierrez@amd.com> | 2016-10-26 22:47:49 -0400 |
| commit | b63eb1302b006682bd227a5e236f7b3b95e9b8e8 (patch) | |
| tree | 87d8422e6bbc7cd88e33d9408e2010c2bdd3c337 /src/gpu-compute/vector_register_file.cc | |
| parent | aa7364276f16bbe6aa300b43bc57ff1b73be42a7 (diff) | |
| download | gem5-b63eb1302b006682bd227a5e236f7b3b95e9b8e8.tar.xz | |
gpu-compute, hsail: pass GPUDynInstPtr to getRegisterIndex()
for HSAIL an operand's indices into the register files may be calculated
trivially, because the operands are always read from a register file, or are
an immediate.
for machine ISA, however, an op selector may specify special registers, or
may specify special SGPRs with an alias op selector value. the location of
some of the special registers values are dependent on the size of the RF
in some cases. here we add a way for the underlying getRegisterIndex()
method to know about the size of the RFs, so that it may find the relative
positions of the special register values.
Diffstat (limited to 'src/gpu-compute/vector_register_file.cc')
| -rw-r--r-- | src/gpu-compute/vector_register_file.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/gpu-compute/vector_register_file.cc b/src/gpu-compute/vector_register_file.cc index c50c06cc6..3c3b400bb 100644 --- a/src/gpu-compute/vector_register_file.cc +++ b/src/gpu-compute/vector_register_file.cc @@ -121,7 +121,7 @@ VectorRegisterFile::operandsReady(Wavefront *w, GPUDynInstPtr ii) const { for (int i = 0; i < ii->getNumOperands(); ++i) { if (ii->isVectorRegister(i)) { - uint32_t vgprIdx = ii->getRegisterIndex(i); + uint32_t vgprIdx = ii->getRegisterIndex(i, ii); uint32_t pVgpr = w->remap(vgprIdx, ii->getOperandSize(i), 1); if (regBusy(pVgpr, ii->getOperandSize(i)) == 1) { @@ -160,7 +160,7 @@ VectorRegisterFile::exec(GPUDynInstPtr ii, Wavefront *w) // iterate over all register destination operands for (int i = 0; i < ii->getNumOperands(); ++i) { if (ii->isVectorRegister(i) && ii->isDstOperand(i)) { - uint32_t physReg = w->remap(ii->getRegisterIndex(i), + uint32_t physReg = w->remap(ii->getRegisterIndex(i, ii), ii->getOperandSize(i), 1); // mark the destination vector register as busy @@ -216,7 +216,7 @@ VectorRegisterFile::updateResources(Wavefront *w, GPUDynInstPtr ii) // iterate over all register destination operands for (int i = 0; i < ii->getNumOperands(); ++i) { if (ii->isVectorRegister(i) && ii->isDstOperand(i)) { - uint32_t physReg = w->remap(ii->getRegisterIndex(i), + uint32_t physReg = w->remap(ii->getRegisterIndex(i, ii), ii->getOperandSize(i), 1); // set the in-flight status of the destination vector register preMarkReg(physReg, ii->getOperandSize(i), 1); |