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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-07 15:04:31 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-07 15:04:31 -0500 |
| commit | 689cab36c90b56b3c8a7cda16d758acdd89f9de1 (patch) | |
| tree | 2f0115320e0a6cfd13e5b054baa0ca13d5655519 /src/kern/tru64/tru64.hh | |
| parent | 329db76e47c825d4ecbe0f5251dbcfaf2ec09516 (diff) | |
| download | gem5-689cab36c90b56b3c8a7cda16d758acdd89f9de1.tar.xz | |
*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
--HG--
extra : convert_revision : f799b65f1b2a6bf43605e6870b0f39b473dc492b
Diffstat (limited to 'src/kern/tru64/tru64.hh')
| -rw-r--r-- | src/kern/tru64/tru64.hh | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/kern/tru64/tru64.hh b/src/kern/tru64/tru64.hh index 6645aa865..b94276035 100644 --- a/src/kern/tru64/tru64.hh +++ b/src/kern/tru64/tru64.hh @@ -511,7 +511,7 @@ class Tru64 : public OperatingSystem tc->setFloatRegBits(i, htog(sc->sc_fpregs[i])); } - tc->setMiscReg(AlphaISA::MISCREG_FPCR, htog(sc->sc_fpcr)); + tc->setMiscRegNoEffect(AlphaISA::MISCREG_FPCR, htog(sc->sc_fpcr)); return 0; } @@ -653,7 +653,7 @@ class Tru64 : public OperatingSystem ssp->nxm_sysevent = htog(0); if (i == 0) { - uint64_t uniq = tc->readMiscReg(AlphaISA::MISCREG_UNIQ); + uint64_t uniq = tc->readMiscRegNoEffect(AlphaISA::MISCREG_UNIQ); ssp->nxm_u.pth_id = htog(uniq + gtoh(attrp->nxm_uniq_offset)); ssp->nxm_u.nxm_active = htog(uniq | 1); } @@ -693,7 +693,7 @@ class Tru64 : public OperatingSystem tc->setIntReg(TheISA::ArgumentReg0, gtoh(attrp->registers.a0)); tc->setIntReg(27/*t12*/, gtoh(attrp->registers.pc)); tc->setIntReg(TheISA::StackPointerReg, gtoh(attrp->registers.sp)); - tc->setMiscReg(AlphaISA::MISCREG_UNIQ, uniq_val); + tc->setMiscRegNoEffect(AlphaISA::MISCREG_UNIQ, uniq_val); tc->setPC(gtoh(attrp->registers.pc)); tc->setNextPC(gtoh(attrp->registers.pc) + sizeof(TheISA::MachInst)); |