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author | Jason Lowe-Power <jason@lowepower.com> | 2017-10-06 14:54:02 -0700 |
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committer | Jason Lowe-Power <jason@lowepower.com> | 2017-12-05 02:09:25 +0000 |
commit | 43a1ea88b89aa3611d3b73cc0d4dc5de3f1f5e6b (patch) | |
tree | b790f98538929d4533a4f79ca04af8bbf4aabf04 /src/learning_gem5/part2/SimpleCache.py | |
parent | 46ec9df617df23d6bb00f6337e61e6d85038ec7e (diff) | |
download | gem5-43a1ea88b89aa3611d3b73cc0d4dc5de3f1f5e6b.tar.xz |
learning_gem5: Adding code for SimpleCache
This is the rest of the code for part 2.
See http://learning.gem5.org/book/part2/simplecache.html
Change-Id: I5db099266a1196914656be3858fdd5fb4f8eab48
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5023
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/learning_gem5/part2/SimpleCache.py')
-rw-r--r-- | src/learning_gem5/part2/SimpleCache.py | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/src/learning_gem5/part2/SimpleCache.py b/src/learning_gem5/part2/SimpleCache.py new file mode 100644 index 000000000..c0cdef9b8 --- /dev/null +++ b/src/learning_gem5/part2/SimpleCache.py @@ -0,0 +1,47 @@ +# -*- coding: utf-8 -*- +# Copyright (c) 2017 Jason Lowe-Power +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Jason Lowe-Power + +from m5.params import * +from m5.proxy import * +from MemObject import MemObject + +class SimpleCache(MemObject): + type = 'SimpleCache' + cxx_header = "learning_gem5/part2/simple_cache.hh" + + # Vector port example. Both the instruction and data ports connect to this + # port which is automatically split out into two ports. + cpu_side = VectorSlavePort("CPU side port, receives requests") + mem_side = MasterPort("Memory side port, sends requests") + + latency = Param.Cycles(1, "Cycles taken on a hit or to resolve a miss") + + size = Param.MemorySize('16kB', "The size of the cache") + + system = Param.System(Parent.any, "The system this cache is part of") |