dev: Scrub out some lingering uses of MemObject.

MemObject doesn't do anything any more, and is basically just an alias
for ClockedObject.

Change-Id: Ic0e1658609e4e1d7f4b829fbc421f222e4869dee
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20719
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

6 files changed, 16 insertions, 13 deletions

diff --git a/src/learning_gem5/part2/SimpleCache.py b/src/learning_gem5/part2/SimpleCache.py
index d0ad261d8..7a02630d2 100644
--- a/src/learning_gem5/part2/SimpleCache.py
+++ b/src/learning_gem5/part2/SimpleCache.py
@@ -29,9 +29,9 @@
 
 from m5.params import *
 from m5.proxy import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
 
-class SimpleCache(MemObject):
+class SimpleCache(ClockedObject):
     type = 'SimpleCache'
     cxx_header = "learning_gem5/part2/simple_cache.hh"
 
diff --git a/src/learning_gem5/part2/SimpleMemobj.py b/src/learning_gem5/part2/SimpleMemobj.py
index e1fb95e22..37694689d 100644
--- a/src/learning_gem5/part2/SimpleMemobj.py
+++ b/src/learning_gem5/part2/SimpleMemobj.py
@@ -28,9 +28,9 @@
 # Authors: Jason Lowe-Power
 
 from m5.params import *
-from m5.objects.MemObject import MemObject
+from m5.SimObject import SimObject
 
-class SimpleMemobj(MemObject):
+class SimpleMemobj(SimObject):
     type = 'SimpleMemobj'
     cxx_header = "learning_gem5/part2/simple_memobj.hh"
 
diff --git a/src/learning_gem5/part2/simple_cache.cc b/src/learning_gem5/part2/simple_cache.cc
index 6deefde53..f6a5f4c9b 100644
--- a/src/learning_gem5/part2/simple_cache.cc
+++ b/src/learning_gem5/part2/simple_cache.cc
@@ -35,7 +35,7 @@
 #include "sim/system.hh"
 
 SimpleCache::SimpleCache(SimpleCacheParams *params) :
-    MemObject(params),
+    ClockedObject(params),
     latency(params->latency),
     blockSize(params->system->cacheLineSize()),
     capacity(params->size / blockSize),
@@ -64,7 +64,7 @@ SimpleCache::getPort(const std::string &if_name, PortID idx)
         return cpuPorts[idx];
     } else {
         // pass it along to our super class
-        return MemObject::getPort(if_name, idx);
+        return ClockedObject::getPort(if_name, idx);
     }
 }
 
@@ -427,7 +427,7 @@ void
 SimpleCache::regStats()
 {
     // If you don't do this you get errors about uninitialized stats.
-    MemObject::regStats();
+    ClockedObject::regStats();
 
     hits.name(name() + ".hits")
         .desc("Number of hits")
diff --git a/src/learning_gem5/part2/simple_cache.hh b/src/learning_gem5/part2/simple_cache.hh
index 56859eb77..173aa0fbb 100644
--- a/src/learning_gem5/part2/simple_cache.hh
+++ b/src/learning_gem5/part2/simple_cache.hh
@@ -33,8 +33,10 @@
 
 #include <unordered_map>
 
-#include "mem/mem_object.hh"
+#include "base/statistics.hh"
+#include "mem/port.hh"
 #include "params/SimpleCache.hh"
+#include "sim/clocked_object.hh"
 
 /**
  * A very simple cache object. Has a fully-associative data store with random
@@ -43,7 +45,7 @@
  * be outstanding at a time.
  * This cache is a writeback cache.
  */
-class SimpleCache : public MemObject
+class SimpleCache : public ClockedObject
 {
   private:
 
diff --git a/src/learning_gem5/part2/simple_memobj.cc b/src/learning_gem5/part2/simple_memobj.cc
index c9af3461f..91110786f 100644
--- a/src/learning_gem5/part2/simple_memobj.cc
+++ b/src/learning_gem5/part2/simple_memobj.cc
@@ -33,7 +33,7 @@
 #include "debug/SimpleMemobj.hh"
 
 SimpleMemobj::SimpleMemobj(SimpleMemobjParams *params) :
-    MemObject(params),
+    SimObject(params),
     instPort(params->name + ".inst_port", this),
     dataPort(params->name + ".data_port", this),
     memPort(params->name + ".mem_side", this),
@@ -55,7 +55,7 @@ SimpleMemobj::getPort(const std::string &if_name, PortID idx)
         return dataPort;
     } else {
         // pass it along to our super class
-        return MemObject::getPort(if_name, idx);
+        return SimObject::getPort(if_name, idx);
     }
 }
 
diff --git a/src/learning_gem5/part2/simple_memobj.hh b/src/learning_gem5/part2/simple_memobj.hh
index 7a9b44764..c08f98e93 100644
--- a/src/learning_gem5/part2/simple_memobj.hh
+++ b/src/learning_gem5/part2/simple_memobj.hh
@@ -31,8 +31,9 @@
 #ifndef __LEARNING_GEM5_PART2_SIMPLE_MEMOBJ_HH__
 #define __LEARNING_GEM5_PART2_SIMPLE_MEMOBJ_HH__
 
-#include "mem/mem_object.hh"
+#include "mem/port.hh"
 #include "params/SimpleMemobj.hh"
+#include "sim/sim_object.hh"
 
 /**
  * A very simple memory object. Current implementation doesn't even cache
@@ -40,7 +41,7 @@
  * This memobj is fully blocking (not non-blocking). Only a single request can
  * be outstanding at a time.
  */
-class SimpleMemobj : public MemObject
+class SimpleMemobj : public SimObject
 {
   private: