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| author | Jason Lowe-Power <jason@lowepower.com> | 2019-04-05 10:29:54 -0700 |
|---|---|---|
| committer | Jason Lowe-Power <jason@lowepower.com> | 2019-04-08 22:51:38 +0000 |
| commit | c1e646d886096ffeca7d9818316ba5e03391898a (patch) | |
| tree | fc6791eee24d6f07dbbdd04cc622eabf108c0d50 /src/learning_gem5 | |
| parent | 36bce3927e589dab1e4b446b75f2cff78cf1f531 (diff) | |
| download | gem5-c1e646d886096ffeca7d9818316ba5e03391898a.tar.xz | |
learning_gem5: Fix vector port panic in SimpleCache
Change-Id: I0f3b71fdbed77690c533d9d14e774ab2cc08c053
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17870
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Diffstat (limited to 'src/learning_gem5')
| -rw-r--r-- | src/learning_gem5/part2/simple_cache.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/learning_gem5/part2/simple_cache.cc b/src/learning_gem5/part2/simple_cache.cc index 880dc39ad..6deefde53 100644 --- a/src/learning_gem5/part2/simple_cache.cc +++ b/src/learning_gem5/part2/simple_cache.cc @@ -54,10 +54,10 @@ SimpleCache::SimpleCache(SimpleCacheParams *params) : Port & SimpleCache::getPort(const std::string &if_name, PortID idx) { - panic_if(idx != InvalidPortID, "This object doesn't support vector ports"); - // This is the name from the Python SimObject declaration in SimpleCache.py if (if_name == "mem_side") { + panic_if(idx != InvalidPortID, + "Mem side of simple cache not a vector port"); return memPort; } else if (if_name == "cpu_side" && idx < cpuPorts.size()) { // We should have already created all of the ports in the constructor |