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| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:49 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:49 -0400 |
| commit | 3b927489371d61ef8b4d0ca9d7a2ca6a5c85f38b (patch) | |
| tree | f05f59c9b737bcb0afd7c0550b7bdfb0ed8bca9b /src/mem/Bridge.py | |
| parent | f25ea3fd569b7616b654be1fc7dabd72493f4ff4 (diff) | |
| download | gem5-3b927489371d61ef8b4d0ca9d7a2ca6a5c85f38b.tar.xz | |
mem: Tidy up the bridge with const and additional checks
This patch does a bit of tidying up in the bridge code, adding const
where appropriate and also removing redundant checks and adding a few
new ones.
There are no changes to the behaviour of any regressions.
Diffstat (limited to 'src/mem/Bridge.py')
| -rw-r--r-- | src/mem/Bridge.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py index 5f2cc9f40..e488871a4 100644 --- a/src/mem/Bridge.py +++ b/src/mem/Bridge.py @@ -1,4 +1,4 @@ -# Copyright (c) 2012 ARM Limited +# Copyright (c) 2012-2013 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -47,8 +47,8 @@ class Bridge(MemObject): cxx_header = "mem/bridge.hh" slave = SlavePort('Slave port') master = MasterPort('Master port') - req_size = Param.Int(16, "The number of requests to buffer") - resp_size = Param.Int(16, "The number of responses to buffer") + req_size = Param.Unsigned(16, "The number of requests to buffer") + resp_size = Param.Unsigned(16, "The number of responses to buffer") delay = Param.Latency('0ns', "The latency of this bridge") ranges = VectorParam.AddrRange([AllMemory], "Address ranges to pass through the bridge") |