MEM: Introduce the master/slave port roles in the Python classes

This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.

The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.

Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.

1 files changed, 2 insertions, 2 deletions

diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py
index 38b344613..ea8684e1b 100644
--- a/src/mem/Bridge.py
+++ b/src/mem/Bridge.py
@@ -31,8 +31,8 @@ from MemObject import MemObject
 
 class Bridge(MemObject):
     type = 'Bridge'
-    slave = Port('Slave port')
-    master = Port('Master port')
+    slave = SlavePort('Slave port')
+    master = MasterPort('Master port')
     req_size = Param.Int(16, "The number of requests to buffer")
     resp_size = Param.Int(16, "The number of requests to buffer")
     delay = Param.Latency('0ns', "The latency of this bridge")