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authorAndreas Hansson <andreas.hansson@arm.com>2014-12-23 09:31:18 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2014-12-23 09:31:18 -0500
commit2f7baf9dbe7fd2cd716885adacf508a5b89e9eb8 (patch)
tree7e758a6d628f67c5407aba0d3d9bca142e3da5c7 /src/mem/Bridge.py
parent381d1da79147fbe8ae62ab4886446bdd7b3c478f (diff)
downloadgem5-2f7baf9dbe7fd2cd716885adacf508a5b89e9eb8.tar.xz
mem: Ensure DRAM controller is idle when in atomic mode
This patch addresses an issue seen with the KVM CPU where the refresh events scheduled by the DRAM controller forces the simulator to switch out of the KVM mode, thus killing performance. The current patch works around the fact that we currently have no proper API to inform a SimObject of the mode switches. Instead we rely on drainResume being called after any switch, and cache the previous mode locally to be able to decide on appropriate actions. The switcheroo regression require a minor stats bump as a result.
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