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| author | Korey Sewell <ksewell@umich.edu> | 2010-01-31 18:26:32 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2010-01-31 18:26:32 -0500 |
| commit | e1fcc6498017574735362636791f9ad73fb39b04 (patch) | |
| tree | da58049ba1b2c6b52dced5aa8928cb6fc27485ab /src/mem/Bridge.py | |
| parent | 4a945aab1958d39fcfea4608715e77d5112809cf (diff) | |
| download | gem5-e1fcc6498017574735362636791f9ad73fb39b04.tar.xz | |
inorder: activate thread on cache miss
-Support ability to activate next ready thread after a cache miss
through the activateNextReadyContext/Thread() functions
-To support this a "readyList" of thread ids is added
-After a cache miss, thread will suspend and then call
activitynextreadythread
Diffstat (limited to 'src/mem/Bridge.py')
0 files changed, 0 insertions, 0 deletions