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authorAndreas Hansson <andreas.hansson@arm.com>2012-08-21 05:49:01 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-08-21 05:49:01 -0400
commit452217817f421a64bc022a5977e795229af45b30 (patch)
tree8f66c1802e5e22cfd4eee963d3cda37b77c5ca08 /src/mem/Bus.py
parent4ebefc145adf818f8695c36a36daacca99f59eb8 (diff)
downloadgem5-452217817f421a64bc022a5977e795229af45b30.tar.xz
Clock: Move the clock and related functions to ClockedObject
This patch moves the clock of the CPU, bus, and numerous devices to the new class ClockedObject, that sits in between the SimObject and MemObject in the class hierarchy. Although there are currently a fair amount of MemObjects that do not make use of the clock, they potentially should do so, e.g. the caches should at some point have the same clock as the CPU, potentially with a 1:n ratio. This patch does not introduce any new clock objects or object hierarchies (clusters, clock domains etc), but is still a step in the direction of having a more structured approach clock domains. The most contentious part of this patch is the serialisation of clocks that some of the modules (but not all) did previously. This serialisation should not be needed as the clock is set through the parameters even when restoring from the checkpoint. In other words, the state is "stored" in the Python code that creates the modules. The nextCycle methods are also simplified and the clock phase parameter of the CPU is removed (this could be part of a clock object once they are introduced).
Diffstat (limited to 'src/mem/Bus.py')
-rw-r--r--src/mem/Bus.py3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mem/Bus.py b/src/mem/Bus.py
index 12657e177..b398af959 100644
--- a/src/mem/Bus.py
+++ b/src/mem/Bus.py
@@ -47,7 +47,8 @@ class BaseBus(MemObject):
abstract = True
slave = VectorSlavePort("vector port for connecting masters")
master = VectorMasterPort("vector port for connecting slaves")
- clock = Param.Clock("1GHz", "bus clock speed")
+ # Override the default clock
+ clock = '1GHz'
header_cycles = Param.Int(1, "cycles of overhead per transaction")
width = Param.Int(8, "bus width (bytes)")
block_size = Param.Int(64, "The default block size if not set by " \