diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-07 12:34:38 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-07 12:34:38 -0400 |
commit | 287ea1a081c5dd3213069755dbbd3d7bf736bacc (patch) | |
tree | e48487569786a562138445d746354b610cf5011f /src/mem/Bus.py | |
parent | 4124ea09f8e2f6934fe746ff7c244dba7230cac9 (diff) | |
download | gem5-287ea1a081c5dd3213069755dbbd3d7bf736bacc.tar.xz |
Param: Transition to Cycles for relevant parameters
This patch is a first step to using Cycles as a parameter type. The
main affected modules are the CPUs and the Ruby caches. There are
definitely plenty more places that are affected, but this patch serves
as a starting point to making the transition.
An important part of this patch is to actually enable parameters to be
specified as Param.Cycles which involves some changes to params.py.
Diffstat (limited to 'src/mem/Bus.py')
-rw-r--r-- | src/mem/Bus.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/Bus.py b/src/mem/Bus.py index b398af959..d24cefa62 100644 --- a/src/mem/Bus.py +++ b/src/mem/Bus.py @@ -49,7 +49,7 @@ class BaseBus(MemObject): master = VectorMasterPort("vector port for connecting slaves") # Override the default clock clock = '1GHz' - header_cycles = Param.Int(1, "cycles of overhead per transaction") + header_cycles = Param.Cycles(1, "cycles of overhead per transaction") width = Param.Int(8, "bus width (bytes)") block_size = Param.Int(64, "The default block size if not set by " \ "any connected module") |