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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:38 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:38 -0400 |
| commit | 1c2ee987f37f4aac16cd0ff3e3ceeff949066a94 (patch) | |
| tree | 4e4e0b02fd0f576d96aa268876a27c413c9a0b48 /src/mem/Bus.py | |
| parent | 8caaac048ae49310b905e190b20459232ae7aa9d (diff) | |
| download | gem5-1c2ee987f37f4aac16cd0ff3e3ceeff949066a94.tar.xz | |
Bus: Make the default bus width 8 bytes instead of 64
This patch changes the default bus width to a more sensible 8 bytes
(64 bits), which is in line with most on-chip buses. Although there
are cases where a wider or narrower bus is useful, the 8 bytes is a
good compromise to serve as the default.
This patch changes essentially all statistics, and will be bundled
with the outstanding changes to the bus.
Diffstat (limited to 'src/mem/Bus.py')
| -rw-r--r-- | src/mem/Bus.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/Bus.py b/src/mem/Bus.py index 05033d382..12657e177 100644 --- a/src/mem/Bus.py +++ b/src/mem/Bus.py @@ -49,7 +49,7 @@ class BaseBus(MemObject): master = VectorMasterPort("vector port for connecting slaves") clock = Param.Clock("1GHz", "bus clock speed") header_cycles = Param.Int(1, "cycles of overhead per transaction") - width = Param.Int(64, "bus width (bytes)") + width = Param.Int(8, "bus width (bytes)") block_size = Param.Int(64, "The default block size if not set by " \ "any connected module") |