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author | Andreas Hansson <andreas.hansson@arm.com> | 2012-02-13 06:43:09 -0500 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-02-13 06:43:09 -0500 |
commit | 5a9a743cfc4517f93e5c94533efa767b92272c59 (patch) | |
tree | f3dbc078a51e5759b26b1a5f16263ddb1cf55a7b /src/mem/Bus.py | |
parent | 8cb4a2208d568eb86ad3f6c6bb250bcbe2952302 (diff) | |
download | gem5-5a9a743cfc4517f93e5c94533efa767b92272c59.tar.xz |
MEM: Introduce the master/slave port roles in the Python classes
This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.
The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.
Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.
Diffstat (limited to 'src/mem/Bus.py')
-rw-r--r-- | src/mem/Bus.py | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mem/Bus.py b/src/mem/Bus.py index fda91742f..91043da80 100644 --- a/src/mem/Bus.py +++ b/src/mem/Bus.py @@ -33,13 +33,14 @@ from MemObject import MemObject class Bus(MemObject): type = 'Bus' - port = VectorPort("vector port for connecting devices") + slave = VectorSlavePort("vector port for connecting masters") + master = VectorMasterPort("vector port for connecting slaves") bus_id = Param.Int(0, "blah") clock = Param.Clock("1GHz", "bus clock speed") header_cycles = Param.Int(1, "cycles of overhead per transaction") width = Param.Int(64, "bus width (bytes)") block_size = Param.Int(64, "The default block size if one isn't set by a device attached to the bus.") - default = \ - Port("Default port for requests that aren't handled by a device.") + default = MasterPort("Default port for requests that aren't handled " \ + "by a device.") use_default_range = \ Param.Bool(False, "Query default port device for legal range.") |