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| author | Omar Naji <Omar.Naji@arm.com> | 2016-10-13 19:22:10 +0100 |
|---|---|---|
| committer | Omar Naji <Omar.Naji@arm.com> | 2016-10-13 19:22:10 +0100 |
| commit | 61b2b493d469e1629437d35e4025bb06a62a85a8 (patch) | |
| tree | df196992b48bfe983d880459be98e1b466b5e027 /src/mem/DRAMCtrl.py | |
| parent | d19dc35b06e803b227531507805f317386c540e6 (diff) | |
| download | gem5-61b2b493d469e1629437d35e4025bb06a62a85a8.tar.xz | |
mem: update DDR3 die revision
Change-Id: I8992ddc1664c3ed4b2d36d8a34e4ce8be113b9de
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Diffstat (limited to 'src/mem/DRAMCtrl.py')
| -rw-r--r-- | src/mem/DRAMCtrl.py | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py index a1d9e2707..8f35f5390 100644 --- a/src/mem/DRAMCtrl.py +++ b/src/mem/DRAMCtrl.py @@ -1,4 +1,4 @@ -# Copyright (c) 2012-2014 ARM Limited +# Copyright (c) 2012-2016 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -376,13 +376,13 @@ class DDR3_1600_x64(DRAMCtrl): # self refresh exit time tXS = '270ns' - # Current values from datasheet - IDD0 = '75mA' - IDD2N = '50mA' - IDD3N = '57mA' - IDD4W = '165mA' - IDD4R = '187mA' - IDD5 = '220mA' + # Current values from datasheet Die Rev E,J + IDD0 = '55mA' + IDD2N = '32mA' + IDD3N = '38mA' + IDD4W = '125mA' + IDD4R = '157mA' + IDD5 = '235mA' VDD = '1.5V' # A single HMC-2500 x32 model based on: |