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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:14:48 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:14:48 -0400 |
| commit | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (patch) | |
| tree | 98c8f6bf612da9a4ab5f721a28366c0bf66a9df8 /src/mem/DRAMCtrl.py | |
| parent | 31f901b69dd2cdc6b6bafa11cfb0af477de57607 (diff) | |
| download | gem5-7e711c98f8fcd949b9430bbf243d60348d0ef28b.tar.xz | |
mem: Increase the default buffer sizes for the DDR4 controller
This patch increases the default read/write buffer sizes for the DDR4
controller config to values that are more suitable for the high
bandwidth and high bank count.
Diffstat (limited to 'src/mem/DRAMCtrl.py')
| -rw-r--r-- | src/mem/DRAMCtrl.py | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py index ef187a31c..d02011526 100644 --- a/src/mem/DRAMCtrl.py +++ b/src/mem/DRAMCtrl.py @@ -522,6 +522,11 @@ class DDR4_2400_x64(DRAMCtrl): # constraints incurred by the bank groups banks_per_rank = 16 + # override the default buffer sizes and go for something larger to + # accommodate the larger bank count + write_buffer_size = 128 + read_buffer_size = 64 + # 1200 MHz tCK = '0.833ns' |