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author | Omar Naji <Omar.Naji@arm.com> | 2014-10-20 18:03:52 -0400 |
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committer | Omar Naji <Omar.Naji@arm.com> | 2014-10-20 18:03:52 -0400 |
commit | 29dd2887f4e1c2ee7689f912c705552afaac4d03 (patch) | |
tree | f54c1d931e92ac574a7ca76c0a774cea5a6482f0 /src/mem/DRAMCtrl.py | |
parent | d2a0f60b69313ad869f81fb006c8e998e40cb3c1 (diff) | |
download | gem5-29dd2887f4e1c2ee7689f912c705552afaac4d03.tar.xz |
mem: Add DRAM device size and check against config
This patch adds the size of the DRAM device to the DRAM config. It
also compares the actual DRAM size (calculated using information from
the config) to the size defined in the system. If these two values do
not match gem5 will print a warning. In order to do correct DRAM
research the size of the memory defined in the system should match the
size of the DRAM in the config. The timing and current parameters
found in the DRAM configs are defined for a DRAM device with a
specific size and would differ for another device with a different
size.
Diffstat (limited to 'src/mem/DRAMCtrl.py')
-rw-r--r-- | src/mem/DRAMCtrl.py | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py index f5b405d09..642e9d525 100644 --- a/src/mem/DRAMCtrl.py +++ b/src/mem/DRAMCtrl.py @@ -96,6 +96,9 @@ class DRAMCtrl(AbstractMemory): max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before " "closing"); + # size of DRAM Chip in Bytes + device_size = Param.MemorySize("Size of DRAM chip") + # pipeline latency of the controller and PHY, split into a # frontend part and a backend part, with reads and writes serviced # by the queues only seeing the frontend contribution, and reads @@ -305,6 +308,9 @@ class DRAMCtrl(AbstractMemory): # timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in # an 8x8 configuration. class DDR3_1600_x64(DRAMCtrl): + # size of device in bytes + device_size = '512MB' + # 8x8 configuration, 8 devices each with an 8-bit interface device_bus_width = 8 @@ -397,6 +403,9 @@ class DDR3_2133_x64(DDR3_1600_x64): # timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M8) # in an 8x8 configuration. class DDR4_2400_x64(DRAMCtrl): + # size of device + device_size = '512MB' + # 8x8 configuration, 8 devices each with an 8-bit interface device_bus_width = 8 @@ -488,6 +497,9 @@ class LPDDR2_S4_1066_x32(DRAMCtrl): # No DLL in LPDDR2 dll = False + # size of device + device_size = '512MB' + # 1x32 configuration, 1 device with a 32-bit interface device_bus_width = 32 @@ -572,6 +584,9 @@ class WideIO_200_x128(DRAMCtrl): # No DLL for WideIO dll = False + # size of device + device_size = '1024MB' + # 1x128 configuration, 1 device with a 128-bit interface device_bus_width = 128 @@ -638,6 +653,9 @@ class LPDDR3_1600_x32(DRAMCtrl): # No DLL for LPDDR3 dll = False + # size of device + device_size = '512MB' + # 1x32 configuration, 1 device with a 32-bit interface device_bus_width = 32 |