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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-02-03 14:25:52 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-02-03 14:25:52 -0500 |
| commit | 5ea60a95b3d87fac6723678e07822aed512f966e (patch) | |
| tree | a104cbcc0e4f15deb4ad87f6642a16ca1145ab0e /src/mem/DRAMCtrl.py | |
| parent | 9aad5b45690adae9f1208b6d3cc8dfc670d54543 (diff) | |
| download | gem5-5ea60a95b3d87fac6723678e07822aed512f966e.tar.xz | |
config: Adjust DRAM channel interleaving defaults
This patch changes the DRAM channel interleaving default behaviour to
be more representative. The default address mapping (RoRaBaCoCh) moves
the channel bits towards the least significant bits, and uses 128 byte
as the default channel interleaving granularity.
These defaults can be overridden if desired, but should serve as a
sensible starting point for most use-cases.
Diffstat (limited to 'src/mem/DRAMCtrl.py')
| -rw-r--r-- | src/mem/DRAMCtrl.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py index 4c500960a..60b3b251e 100644 --- a/src/mem/DRAMCtrl.py +++ b/src/mem/DRAMCtrl.py @@ -92,7 +92,7 @@ class DRAMCtrl(AbstractMemory): # scheduler, address map and page policy mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") - addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy") + addr_mapping = Param.AddrMap('RoRaBaCoCh', "Address mapping policy") page_policy = Param.PageManage('open_adaptive', "Page management policy") # enforce a limit on the number of accesses per row |