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| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2019-09-12 16:10:26 +0100 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2019-10-29 09:48:10 +0000 |
| commit | 39220ef3681deb8c224cdcf28efdaa74bfa2facd (patch) | |
| tree | 58552932697f996b2a30ab336a862dd03b9a4619 /src/mem/DRAMCtrl.py | |
| parent | 12cf816745fa9fe2718e54d19b33f303b15b90aa (diff) | |
| download | gem5-39220ef3681deb8c224cdcf28efdaa74bfa2facd.tar.xz | |
mem: Fix DRAM controller to operate on its own address space
Typically, a memory controller is assigned an address range of the
form [start, end). This address range might be interleaved and
therefore only a non-continuous subset of the addresses in the address
range is handed by this controller.
Prior to this patch, the DRAM controller was unaware of the
interleaving and as a result the address range could affect the
mapping of addresses to DRAM ranks, rows and columns. This patch
changes the DRAM controller, to transform the input address to a
continuous range of the form [0, size). As a result the DRAM
controller always operates on a dense and continuous address range
regardlesss of the system configuration.
Change-Id: I7d273a630928421d1854658c9bb0ab34e9360851
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19328
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/mem/DRAMCtrl.py')
| -rw-r--r-- | src/mem/DRAMCtrl.py | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py index 14db3d3c9..4ed4e50d1 100644 --- a/src/mem/DRAMCtrl.py +++ b/src/mem/DRAMCtrl.py @@ -1,4 +1,4 @@ -# Copyright (c) 2012-2018 ARM Limited +# Copyright (c) 2012-2019 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -130,10 +130,6 @@ class DRAMCtrl(QoSMemCtrl): # update per memory class when bank group architecture is supported bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank") banks_per_rank = Param.Unsigned("Number of banks per rank") - # only used for the address mapping as the controller by - # construction is a single channel and multiple controllers have - # to be instantiated for a multi-channel configuration - channels = Param.Unsigned(1, "Number of channels") # Enable DRAM powerdown states if True. This is False by default due to # performance being lower when enabled |