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authorAndreas Hansson <andreas.hansson@arm.com>2016-08-12 14:11:45 +0100
committerAndreas Hansson <andreas.hansson@arm.com>2016-08-12 14:11:45 +0100
commit94f94fbc555356d15c4f06aeb1a1fb5da53c365f (patch)
tree6b1e88dfa13de7f59bf220f09c533e917b766e74 /src/mem/DRAMSim2.py
parent25095534039245002b7e529eaa9ddef01a84d059 (diff)
downloadgem5-94f94fbc555356d15c4f06aeb1a1fb5da53c365f.tar.xz
mem: Update mostly exclusive cache policy to cover more cases
This patch changes how the mostly exclusive policy is enforced to ensure that we drop blocks when we should. As part of this change, the actual invalidation due to the clusivity enforcement is moved outside the hit handling, to a separate method maintainClusivity. For the timing mode that means we can deal with all MSHR targets before taking any action and possibly dropping the block. The method satisfyCpuSideRequest is also renamed satisfyRequest as part of this change (since we only ever see requests from the cpu-side port). Change-Id: If6f3d1e0c3e7be9a67b72a55e4fc2ec4a90fd3d2 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
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