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author | Andreas Sandberg <andreas.sandberg@arm.com> | 2018-05-02 13:55:10 +0100 |
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committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2018-06-28 16:12:53 +0000 |
commit | 0f33b2c1d5875aae036a9e2779f6e9c764e0f85e (patch) | |
tree | 659285bb368acc6b5f93ef4ac52b1d3678a1a211 /src/mem/MemDelay.py | |
parent | f6dd997ef43f52f80f5cdb43cd32614ce4169960 (diff) | |
download | gem5-0f33b2c1d5875aae036a9e2779f6e9c764e0f85e.tar.xz |
mem: Add a memory delay simulator
Add a memory system component that delays traffic. The base
functionality to delay packets is implemented in the abstract MemDelay
class. This class exposes three methods that control packet delays:
* delayReq(pkt)
* delayResp(pkt)
* delaySnoopResp(pkt)
These methods should be specialized to implement delays for specific
packet types.
The class SimpleMemDelay uses the MemDelay base class to implement
constant delays for read/write requests and responses.
The intention is that these classes can be used for rapid prototyping
of components that add a small fixed delay and the same throughput as
the interconnect. I.e., any buffering done in the base class will be
small and proportional to the introduced delay.
Change-Id: I158cb85f20e32bfdbcbfed66a785b4b2dd47b628
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nicholas Lindsey <nicholas.lindsay@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11521
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/mem/MemDelay.py')
-rw-r--r-- | src/mem/MemDelay.py | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/src/mem/MemDelay.py b/src/mem/MemDelay.py new file mode 100644 index 000000000..b48866815 --- /dev/null +++ b/src/mem/MemDelay.py @@ -0,0 +1,57 @@ +# Copyright (c) 2018 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Andreas Sandberg + +from m5.params import * +from MemObject import MemObject + +class MemDelay(MemObject): + type = 'MemDelay' + cxx_header = 'mem/mem_delay.hh' + abstract = True + + master = MasterPort("Master port") + slave = SlavePort("Slave port") + +class SimpleMemDelay(MemDelay): + type = 'SimpleMemDelay' + cxx_header = 'mem/mem_delay.hh' + + read_req = Param.Latency("0t", "Read request delay") + read_resp = Param.Latency("0t", "Read response delay") + + write_req = Param.Latency("0t", "Write request delay") + write_resp = Param.Latency("0t", "Write response delay") |