summaryrefslogtreecommitdiff
path: root/src/mem/MemObject.py
diff options
context:
space:
mode:
authorAndreas Hansson <andreas.hansson@arm.com>2013-03-01 13:20:19 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2013-03-01 13:20:19 -0500
commitcafd38f36c4d71c3f3d6efaf0023aec2cfc51b32 (patch)
tree713f70f114707f5cd8765937c44e03f87ec0df01 /src/mem/MemObject.py
parentc636a09e83b08c27ce60a0f1d13536d736a06926 (diff)
downloadgem5-cafd38f36c4d71c3f3d6efaf0023aec2cfc51b32.tar.xz
mem: Merge ranges in bus before passing them on
This patch adds basic merging of address ranges to the bus, such that interleaved ranges are merged together before being passed on by the bus. As such, the bus aggregates the address ranges of the connected slave ports and then passes on the merged ranges through its master ports. The bus thus hides the complexity of the interleaved ranges and only exposes contigous ranges to the surrounding system. As part of this patch, the bus ranges are also cached for any future queries.
Diffstat (limited to 'src/mem/MemObject.py')
0 files changed, 0 insertions, 0 deletions