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| author | Brad Beckmann <Brad.Beckmann@amd.com> | 2009-11-18 13:55:58 -0800 |
|---|---|---|
| committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2009-11-18 13:55:58 -0800 |
| commit | 90d6e2652fc8590116d436a1143700e11893cfa4 (patch) | |
| tree | 47b58a565a62897fd9fd0d4184409ad1f4c0f713 /src/mem/RubyMemory.py | |
| parent | dce53610c374eba2a8dae236a13b3197cd42edc6 (diff) | |
| download | gem5-90d6e2652fc8590116d436a1143700e11893cfa4.tar.xz | |
ruby: included ruby config parameter ports per core
Slightly improved the major hack need to correctly assign the number of ports
per core. CPUs have two ports: icache + dcache. MemTester has one port.
Diffstat (limited to 'src/mem/RubyMemory.py')
| -rw-r--r-- | src/mem/RubyMemory.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/RubyMemory.py b/src/mem/RubyMemory.py index ddd97572c..2ad794a3f 100644 --- a/src/mem/RubyMemory.py +++ b/src/mem/RubyMemory.py @@ -45,3 +45,4 @@ class RubyMemory(PhysicalMemory): num_dmas = Param.Int(0, "Number of DMA ports connected to the Ruby memory") dma_port = VectorPort("Ruby_dma_ports") pio_port = Port("Ruby_pio_port") + ports_per_core = Param.Int(2, "Number of per core. Typical two: icache + dcache") |