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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:12 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:12 -0400 |
| commit | 7c18691db1bc450b04142502e5c324ad612318ab (patch) | |
| tree | 10083265e3854227c8946f861db127c7d783f2e0 /src/mem/SConscript | |
| parent | 3dd1587afc48e8d2b870253de689bbe7262fcbe6 (diff) | |
| download | gem5-7c18691db1bc450b04142502e5c324ad612318ab.tar.xz | |
mem: Rename SimpleDRAM to a more suitable DRAMCtrl
This patch renames the not-so-simple SimpleDRAM to a more suitable
DRAMCtrl. The name change is intended to ensure that we do not send
the wrong message (although the "simple" in SimpleDRAM was originally
intended as in cleverly simple, or elegant).
As the DRAM controller modelling work is being presented at ISPASS'14
our hope is that a broader audience will use the model in the future.
--HG--
rename : src/mem/SimpleDRAM.py => src/mem/DRAMCtrl.py
rename : src/mem/simple_dram.cc => src/mem/dram_ctrl.cc
rename : src/mem/simple_dram.hh => src/mem/dram_ctrl.hh
Diffstat (limited to 'src/mem/SConscript')
| -rw-r--r-- | src/mem/SConscript | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/SConscript b/src/mem/SConscript index ddd57d11b..c513004d2 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -40,15 +40,16 @@ SimObject('AbstractMemory.py') SimObject('AddrMapper.py') SimObject('Bridge.py') SimObject('Bus.py') +SimObject('DRAMCtrl.py') SimObject('MemObject.py') SimObject('SimpleMemory.py') -SimObject('SimpleDRAM.py') Source('abstract_mem.cc') Source('addr_mapper.cc') Source('bridge.cc') Source('bus.cc') Source('coherent_bus.cc') +Source('dram_ctrl.cc') Source('mem_object.cc') Source('mport.cc') Source('noncoherent_bus.cc') @@ -59,7 +60,6 @@ Source('tport.cc') Source('port_proxy.cc') Source('simple_mem.cc') Source('physical.cc') -Source('simple_dram.cc') if env['TARGET_ISA'] != 'null': Source('fs_translating_port_proxy.cc') |