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| author | Erfan Azarkhish <erfan.azarkhish@unibo.it> | 2015-11-03 12:17:57 -0600 |
|---|---|---|
| committer | Erfan Azarkhish <erfan.azarkhish@unibo.it> | 2015-11-03 12:17:57 -0600 |
| commit | 7e3f670457d2705c97078d6a20ee263fabd21ef4 (patch) | |
| tree | 48e63ee4bd5e06b03f2b03017979ce48a52312be /src/mem/SConscript | |
| parent | 1530e1a690a7d3c1b028e59d2fa37c88df8e47df (diff) | |
| download | gem5-7e3f670457d2705c97078d6a20ee263fabd21ef4.tar.xz | |
mem: hmc: serial link model
This changeset adds a serial link model for the Hybrid Memory Cube (HMC).
SerialLink is a simple variation of the Bridge class, with the ability to
account for the latency of packet serialization. Also trySendTiming has been
modified to correctly model bandwidth.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/mem/SConscript')
| -rw-r--r-- | src/mem/SConscript | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mem/SConscript b/src/mem/SConscript index 3b65131a2..1d3249918 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -43,6 +43,7 @@ SimObject('MemObject.py') SimObject('SimpleMemory.py') SimObject('XBar.py') SimObject('HMCController.py') +SimObject('SerialLink.py') Source('abstract_mem.cc') Source('addr_mapper.cc') @@ -66,6 +67,7 @@ Source('stack_dist_calc.cc') Source('tport.cc') Source('xbar.cc') Source('hmc_controller.cc') +Source('serial_link.cc') if env['TARGET_ISA'] != 'null': Source('fs_translating_port_proxy.cc') @@ -104,6 +106,7 @@ DebugFlag('PacketQueue') DebugFlag('StackDist') DebugFlag("DRAMSim2") DebugFlag('HMCController') +DebugFlag('SerialLink') DebugFlag("MemChecker") DebugFlag("MemCheckerMonitor") |