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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-09-25 11:49:40 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-09-25 11:49:40 -0500 |
| commit | 396600de107220db8c2c8f3951eeb7062ac0e81c (patch) | |
| tree | c5c1d81488c543d02a3d1547213c21ddd906edc3 /src/mem/SConscript | |
| parent | 0c99d21ad748371e801508a8c3652e07e2e56f93 (diff) | |
| download | gem5-396600de107220db8c2c8f3951eeb7062ac0e81c.tar.xz | |
mem: Add a gasket that allows memory ranges to be re-mapped.
For example if DRAM is at two locations and mirrored this patch allows the
mirroring to occur.
Diffstat (limited to 'src/mem/SConscript')
| -rw-r--r-- | src/mem/SConscript | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mem/SConscript b/src/mem/SConscript index 1c43975df..9cf8b08d1 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -30,11 +30,13 @@ Import('*') +SimObject('AddrMapper.py') SimObject('Bridge.py') SimObject('Bus.py') SimObject('CommMonitor.py') SimObject('MemObject.py') +Source('addr_mapper.cc') Source('bridge.cc') Source('bus.cc') Source('coherent_bus.cc') |