mem: Add a wrapped DRAMSim2 memory controller

This patch adds DRAMSim2 as a memory controller by wrapping the
external library and creating a sublass of AbstractMemory that bridges
between the semantics of gem5 and the DRAMSim2 interface.

The DRAMSim2 wrapper extracts the clock period from the config
file. There is no way of extracting this information from DRAMSim2
itself, so we simply read the same config file and get it from there.

To properly model the response queue, the wrapper keeps track of how
many transactions are in the actual controller, and how many are
stacking up waiting to be sent back as responses (in the wrapper). The
latter requires us to move away from the queued port and manage the
packets ourselves. This is due to DRAMSim2 not having any flow control
on the response path.

DRAMSim2 assumes that the transactions it is given are matching the
burst size of the choosen memory. The wrapper checks to ensure the
cache line size of the system matches the burst size of DRAMSim2 as
there are currently no provisions to split the system requests. In
theory we could allow a cache line size smaller than the burst size,
but that would lead to inefficient use of the DRAM, so for not we
fatal also in this case.

1 files changed, 7 insertions, 0 deletions

diff --git a/src/mem/SConscript b/src/mem/SConscript
index 90b49067e..9096fad5c 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -66,6 +66,11 @@ if env['TARGET_ISA'] != 'null':
     Source('se_translating_port_proxy.cc')
     Source('page_table.cc')
 
+    if env['HAVE_DRAMSIM']:
+        SimObject('DRAMSim2.py')
+        Source('dramsim2_wrapper.cc')
+        Source('dramsim2.cc')
+
 DebugFlag('BaseBus')
 DebugFlag('BusAddrRanges')
 DebugFlag('CoherentBus')
@@ -81,6 +86,8 @@ DebugFlag('MMU')
 DebugFlag('MemoryAccess')
 DebugFlag('PacketQueue')
 
+DebugFlag("DRAMSim2")
+
 DebugFlag('ProtocolTrace')
 DebugFlag('RubyCache')
 DebugFlag('RubyCacheTrace')