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| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-07-18 08:31:16 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-07-18 08:31:16 -0400 |
| commit | d4273cc9a6f3c00566e97ebcd71509ed14477b37 (patch) | |
| tree | 9b50625fc5d2bb457a959f379a45687903660237 /src/mem/SimpleDRAM.py | |
| parent | 4e8ecd7c6fd0447f563179b5a8fdbb13b562ca9e (diff) | |
| download | gem5-d4273cc9a6f3c00566e97ebcd71509ed14477b37.tar.xz | |
mem: Set the cache line size on a system level
This patch removes the notion of a peer block size and instead sets
the cache line size on the system level.
Previously the size was set per cache, and communicated through the
interconnect. There were plenty checks to ensure that everyone had the
same size specified, and these checks are now removed. Another benefit
that is not yet harnessed is that the cache line size is now known at
construction time, rather than after the port binding. Hence, the
block size can be locally stored and does not have to be queried every
time it is used.
A follow-on patch updates the configuration scripts accordingly.
Diffstat (limited to 'src/mem/SimpleDRAM.py')
| -rw-r--r-- | src/mem/SimpleDRAM.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/SimpleDRAM.py b/src/mem/SimpleDRAM.py index 64e9f272b..ec76542d8 100644 --- a/src/mem/SimpleDRAM.py +++ b/src/mem/SimpleDRAM.py @@ -170,7 +170,7 @@ class SimpleDRAM(AbstractMemory): # tRC - assumed to be 4 * tRP - # burst length for an access derived from peerBlockSize + # burst length for an access derived from the cache line size # A single DDR3 x64 interface (one command and address bus), with # default timings based on DDR3-1600 4 Gbit parts in an 8x8 |