mem: Add tTAW and tFAW to the SimpleDRAM model

This patch adds two additional scheduling constraints to the DRAM
controller model, to constrain the activation rate. The two metrics
are determine the size of the activation window in terms of the number
of activates and the minimum time required for that number of
activates. This maps to current DDRx, LPDDRx and WIOx standards that
have either tFAW (4 activate window) or tTAW (2 activate window)
scheduling constraints.

1 files changed, 6 insertions, 8 deletions

diff --git a/src/mem/SimpleDRAM.py b/src/mem/SimpleDRAM.py
index 3211f576a..83eaac611 100644
--- a/src/mem/SimpleDRAM.py
+++ b/src/mem/SimpleDRAM.py
@@ -112,7 +112,12 @@ class SimpleDRAM(AbstractMemory):
     # write-to-read turn around penalty, assumed same as read-to-write
     tWTR = Param.Latency("1ns", "Write to read switching time")
 
-    # Currently unimplemented, unused, deduced or rolled into other params
+    # time window in which a maximum number of activates are allowed
+    # to take place, set to 0 to disable
+    tXAW = Param.Latency("0ns", "X activation window")
+    activation_limit = Param.Unsigned(4, "Max number of activates in window")
+
+    # Currently rolled into other params
     ######################################################################
 
     # the minimum amount of time between a row being activated, and
@@ -122,10 +127,3 @@ class SimpleDRAM(AbstractMemory):
     # tRC  - assumed to be 4 * tRP
 
     # burst length for an access derived from peerBlockSize
-
-    # @todo: Implement tFAW in the model
-    # minimum time window in which a maximum of four activates are
-    # allowed to take place
-    # tFAW = Param.Latency("30ns", "Four activation window")
-
-