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authorWendy Elsasser <wendy.elsasser@arm.com>2014-03-23 11:12:08 -0400
committerWendy Elsasser <wendy.elsasser@arm.com>2014-03-23 11:12:08 -0400
commitbbbae677ed179c819db124a54a7a011df042ef85 (patch)
treeaeb89fbae0e278da9c8b0bcb8cf689a1f4848bb4 /src/mem/SimpleDRAM.py
parent03a1aed803ed0d8510a5cf76994b203d3ca3af02 (diff)
downloadgem5-bbbae677ed179c819db124a54a7a011df042ef85.tar.xz
mem: Add close adaptive paging policy to DRAM controller model
This patch adds a second adaptive page policy to the DRAM controller, closing the page unless there are already queued accesses to the open page.
Diffstat (limited to 'src/mem/SimpleDRAM.py')
-rw-r--r--src/mem/SimpleDRAM.py6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/mem/SimpleDRAM.py b/src/mem/SimpleDRAM.py
index a72bd518c..514ff3664 100644
--- a/src/mem/SimpleDRAM.py
+++ b/src/mem/SimpleDRAM.py
@@ -54,8 +54,10 @@ class MemSched(Enum): vals = ['fcfs', 'frfcfs']
# maximises parallelism.
class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
-# Enum for the page policy, either open, open_adaptive or close.
-class PageManage(Enum): vals = ['open', 'open_adaptive', 'close']
+# Enum for the page policy, either open, open_adaptive, close, or
+# close_adaptive.
+class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
+ 'close_adaptive']
# SimpleDRAM is a single-channel single-ported DRAM controller model
# that aims to model the most important system-level performance