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authorAndreas Hansson <andreas.hansson@arm.com>2013-08-19 03:52:25 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2013-08-19 03:52:25 -0400
commit2a675aecb904143327befde70704d87c85fe7ea5 (patch)
tree7d08e554bcbf6959316a7174e46a755009026894 /src/mem/SimpleMemory.py
parent9b2effd9e2d30c5e2a72bfe78214cd88689d89d9 (diff)
downloadgem5-2a675aecb904143327befde70704d87c85fe7ea5.tar.xz
mem: Add an internal packet queue in SimpleMemory
This patch adds a packet queue in SimpleMemory to avoid using the packet queue in the port (and thus have no involvement in the flow control). The port queue was bound to 100 packets, and as the SimpleMemory is modelling both a controller and an actual RAM, it potentially has a large number of packets in flight. There is currently no limit on the number of packets in the memory controller, but this could easily be added in a follow-on patch. As a result of the added internal storage, the functional access and draining is updated. Some minor cleaning up and renaming has also been done. The memtest regression changes as a result of this patch and the stats will be updated.
Diffstat (limited to 'src/mem/SimpleMemory.py')
-rw-r--r--src/mem/SimpleMemory.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/SimpleMemory.py b/src/mem/SimpleMemory.py
index 0cf6dece3..0a90eaa7c 100644
--- a/src/mem/SimpleMemory.py
+++ b/src/mem/SimpleMemory.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012-2013 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall