mem: Add snoop filters to L2 crossbars, and check size

This patch adds a snoop filter to the L2XBar. For now we refrain from
globally adding a snoop filter to the SystemXBar, since the latter is
also used in systems without caches. In scenarios without caches the
snoop filter will not see any writeback/clean evicts from the CPU
ports, despite the fact that they are snooping. To avoid inadvertent
use of the snoop filter in these cases we leave it out for now.

A size check is added to the snoop filter, merely to ensure it does
not grow beyond the total capacity of the caches above it. The size
has to be set manually, and a value of 8 MByte is choosen as suitably
high default.

1 files changed, 8 insertions, 0 deletions

diff --git a/src/mem/XBar.py b/src/mem/XBar.py
index a445b5e37..8614519b3 100644
--- a/src/mem/XBar.py
+++ b/src/mem/XBar.py
@@ -112,6 +112,9 @@ class SnoopFilter(SimObject):
 
     system = Param.System(Parent.any, "System that the crossbar belongs to.")
 
+    # Sanity check on max capacity to track, adjust if needed.
+    max_capacity = Param.MemorySize('8MB', "Maximum capacity of snoop filter")
+
 # We use a coherent crossbar to connect multiple masters to the L2
 # caches. Normally this crossbar would be part of the cache itself.
 class L2XBar(CoherentXBar):
@@ -125,6 +128,11 @@ class L2XBar(CoherentXBar):
     response_latency = 1
     snoop_response_latency = 1
 
+    # Use a snoop-filter by default, and set the latency to zero as
+    # the lookup is assumed to overlap with the frontend latency of
+    # the crossbar
+    snoop_filter = SnoopFilter(lookup_latency = 0)
+
 # One of the key coherent crossbar instances is the system
 # interconnect, tying together the CPU clusters, GPUs, and any I/O
 # coherent masters, and DRAM controllers.