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author | Wendy Elsasser <wendy.elsasser@arm.com> | 2016-10-13 19:22:11 +0100 |
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committer | Wendy Elsasser <wendy.elsasser@arm.com> | 2016-10-13 19:22:11 +0100 |
commit | 0dd0d4ee7adb561e89a47c3e8284c237bebdc4ab (patch) | |
tree | a82aca322b5ba7be0bb924c7c12424aaeae39f15 /src/mem/abstract_mem.cc | |
parent | 27665af26d8bfdeaab3f3877da9158c9fc5f93ac (diff) | |
download | gem5-0dd0d4ee7adb561e89a47c3e8284c237bebdc4ab.tar.xz |
mem: Modify drain to ensure banks and power are idled
Add constraint that all ranks have to be in PWR_IDLE
before signaling drain complete
This will ensure that the banks are all closed and the rank
has exited any low-power states.
On suspend, update the power stats to sync the DRAM power logic
The logic maintains the location of the signalDrainDone
method, which is still triggered from either:
1) Read response event
2) Next request event
This ensures that the drain will complete in the READ bus
state and minimizes the changes required.
Change-Id: If1476e631ea7d5999fe50a0c9379c5967a90e3d1
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Diffstat (limited to 'src/mem/abstract_mem.cc')
0 files changed, 0 insertions, 0 deletions