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authorAndreas Hansson <andreas.hansson@arm.com>2012-09-18 10:30:02 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-09-18 10:30:02 -0400
commit7c55464aac2bcab15699e563f18a7d3d565d949a (patch)
treebb507025ea2dc209b9d80367665ea3af682b4146 /src/mem/abstract_mem.cc
parentd1f3a3b91a2370c5e8fae2951a3ee6231158d4f4 (diff)
downloadgem5-7c55464aac2bcab15699e563f18a7d3d565d949a.tar.xz
Mem: Add a maximum bandwidth to SimpleMemory
This patch makes a minor addition to the SimpleMemory by enforcing a maximum data rate. The bandwidth is configurable, and a reasonable value (12.8GB/s) has been choosen as the default. The changes do add some complexity to the SimpleMemory, but they should definitely be justifiable as this enables a far more realistic setup using even this simple memory controller. The rate regulation is done for reads and writes combined to reflect the bidirectional data busses used by most (if not all) relevant memories. Moreover, the regulation is done per packet as opposed to long term, as it is the short term data rate (data bus width times frequency) that is the limiting factor. A follow-up patch bumps the stats for the regressions.
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