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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:39 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:39 -0400 |
| commit | b265d9925c123f0df50db98cf56dab6a3596b54b (patch) | |
| tree | 2b115ce862733a499c453352db3a6ae5b9f93cd6 /src/mem/bridge.cc | |
| parent | 1c2ee987f37f4aac16cd0ff3e3ceeff949066a94 (diff) | |
| download | gem5-b265d9925c123f0df50db98cf56dab6a3596b54b.tar.xz | |
Port: Align port names in C++ and Python
This patch is a first step to align the port names used in the Python
world and the C++ world. Ultimately it serves to make the use of
config.json together with output from the simulation easier, including
post-processing of statistics.
Most notably, the CPU, cache, and bus is addressed in this patch, and
there might be other ports that should be updated accordingly. The
dash name separator has also been replaced with a "." which is what is
used to concatenate the names in python, and a separation is made
between the master and slave port in the bus.
Diffstat (limited to 'src/mem/bridge.cc')
| -rw-r--r-- | src/mem/bridge.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc index 3a5313e7b..e9dc68a03 100644 --- a/src/mem/bridge.cc +++ b/src/mem/bridge.cc @@ -79,9 +79,9 @@ Bridge::BridgeMasterPort::BridgeMasterPort(const std::string &_name, Bridge::Bridge(Params *p) : MemObject(p), - slavePort(p->name + "-slave", this, masterPort, p->delay, + slavePort(p->name + ".slave", this, masterPort, p->delay, p->nack_delay, p->resp_size, p->ranges), - masterPort(p->name + "-master", this, slavePort, p->delay, p->req_size), + masterPort(p->name + ".master", this, slavePort, p->delay, p->req_size), ackWrites(p->write_ack), _params(p) { if (ackWrites) |