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authorWilliam Wang <william.wang@arm.com>2012-03-30 09:40:11 -0400
committerWilliam Wang <william.wang@arm.com>2012-03-30 09:40:11 -0400
commitf9d403a7b95c50a8b75f8442101eb87ca465f967 (patch)
treea8302eb02dd5947d53b9437cc19d552145267189 /src/mem/bridge.cc
parenta14013af3a9e04d68985aea7bcff6c1e70bdbb82 (diff)
downloadgem5-f9d403a7b95c50a8b75f8442101eb87ca465f967.tar.xz
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++ code, thus bringing the previous classification from the Python classes into the corresponding simulation objects and memory objects. The patch enables us to classify behaviours into the two bins and add assumptions and enfore compliance, also simplifying the two interfaces. As a starting point, isSnooping is confined to a master port, and getAddrRanges to slave ports. More of these specilisations are to come in later patches. The getPort function is not getMasterPort and getSlavePort, and returns a port reference rather than a pointer as NULL would never be a valid return value. The default implementation of these two functions is placed in MemObject, and calls fatal. The one drawback with this specific patch is that it requires some code duplication, e.g. QueuedPort becomes QueuedMasterPort and QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort (avoiding multiple inheritance). With the later introduction of the port interfaces, moving the functionality outside the port itself, a lot of the duplicated code will disappear again.
Diffstat (limited to 'src/mem/bridge.cc')
-rw-r--r--src/mem/bridge.cc45
1 files changed, 19 insertions, 26 deletions
diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index 0733b6ea8..ebb37e792 100644
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2011-2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -59,7 +59,7 @@ Bridge::BridgeSlavePort::BridgeSlavePort(const std::string &_name,
int _delay, int _nack_delay,
int _resp_limit,
std::vector<Range<Addr> > _ranges)
- : Port(_name, _bridge), bridge(_bridge), masterPort(_masterPort),
+ : SlavePort(_name, _bridge), bridge(_bridge), masterPort(_masterPort),
delay(_delay), nackDelay(_nack_delay),
ranges(_ranges.begin(), _ranges.end()),
outstandingResponses(0), inRetry(false),
@@ -71,7 +71,7 @@ Bridge::BridgeMasterPort::BridgeMasterPort(const std::string &_name,
Bridge* _bridge,
BridgeSlavePort& _slavePort,
int _delay, int _req_limit)
- : Port(_name, _bridge), bridge(_bridge), slavePort(_slavePort),
+ : MasterPort(_name, _bridge), bridge(_bridge), slavePort(_slavePort),
delay(_delay), inRetry(false), reqQueueLimit(_req_limit),
sendEvent(*this)
{
@@ -88,19 +88,25 @@ Bridge::Bridge(Params *p)
panic("No support for acknowledging writes\n");
}
-Port*
-Bridge::getPort(const std::string &if_name, int idx)
+MasterPort&
+Bridge::getMasterPort(const std::string &if_name, int idx)
{
- if (if_name == "slave")
- return &slavePort;
- else if (if_name == "master")
- return &masterPort;
- else {
- panic("Bridge %s has no port named %s\n", name(), if_name);
- return NULL;
- }
+ if (if_name == "master")
+ return masterPort;
+ else
+ // pass it along to our super class
+ return MemObject::getMasterPort(if_name, idx);
}
+SlavePort&
+Bridge::getSlavePort(const std::string &if_name, int idx)
+{
+ if (if_name == "slave")
+ return slavePort;
+ else
+ // pass it along to our super class
+ return MemObject::getSlavePort(if_name, idx);
+}
void
Bridge::init()
@@ -473,19 +479,6 @@ Bridge::BridgeMasterPort::checkFunctional(PacketPtr pkt)
return found;
}
-/** Function called by the port when the bridge is receiving a range change.*/
-void
-Bridge::BridgeMasterPort::recvRangeChange()
-{
- // no need to forward as the bridge has a fixed set of ranges
-}
-
-void
-Bridge::BridgeSlavePort::recvRangeChange()
-{
- // is a slave port so do nothing
-}
-
AddrRangeList
Bridge::BridgeSlavePort::getAddrRanges()
{