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author | Andreas Sandberg <andreas.sandberg@arm.com> | 2015-08-07 09:59:26 +0100 |
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committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2015-08-07 09:59:26 +0100 |
commit | ce8939a97e26eb96cfe0604e737c0b155ba07656 (patch) | |
tree | f33826ffc01240ace3d5756f87014ce9b7899165 /src/mem/bridge.cc | |
parent | 598edaae0509c455e06e1689fd3c50caaeef0f30 (diff) | |
download | gem5-ce8939a97e26eb96cfe0604e737c0b155ba07656.tar.xz |
dev: Implement a simple display timing generator
Timing generator for a pixel-based display. The timing generator is
intended for display processors driving a standard rasterized
display. The simplest possible display processor needs to derive from
this class and override the nextPixel() method to feed the display
with pixel data.
Pixels are ordered relative to the top left corner of the
display. Scan lines appear in the following order:
* Vertical Sync (starting at line 0)
* Vertical back porch
* Visible lines
* Vertical front porch
Pixel order within a scan line:
* Horizontal Sync
* Horizontal Back Porch
* Visible pixels
* Horizontal Front Porch
All events in the timing generator are automatically suspended on a
drain() request and restarted on drainResume(). This is conceptually
equivalent to clock gating when the pixel clock while the system is
draining. By gating the pixel clock, we prevent display controllers
from disturbing a memory system that is about to drain.
Diffstat (limited to 'src/mem/bridge.cc')
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