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author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-09 14:40:19 -0400 |
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committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-09 14:40:19 -0400 |
commit | 6dc599ea9bae9cb56ca81094b37009f5a14ebdff (patch) | |
tree | 6fa3f64eaff474822ebb1917c87f1413bea43e00 /src/mem/bridge.cc | |
parent | 71aca6d29e686ecdec2828c8be1989f74d9b28d3 (diff) | |
download | gem5-6dc599ea9bae9cb56ca81094b37009f5a14ebdff.tar.xz |
mem: fix functional accesses to deal with coherence change
We can't just obliviously return the first valid cache block
we find any more... see comments for details.
Diffstat (limited to 'src/mem/bridge.cc')
-rw-r--r-- | src/mem/bridge.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc index d0135fc9d..668b492e8 100644 --- a/src/mem/bridge.cc +++ b/src/mem/bridge.cc @@ -325,8 +325,10 @@ Bridge::BridgePort::recvFunctional(PacketPtr pkt) pkt->pushLabel(name()); for (i = sendQueue.begin(); i != sendQueue.end(); ++i) { - if (pkt->checkFunctional((*i)->pkt)) + if (pkt->checkFunctional((*i)->pkt)) { + pkt->makeResponse(); return; + } } pkt->popLabel(); |