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| author | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-19 21:26:46 -0400 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-19 21:26:46 -0400 |
| commit | 780aa0a0ebb765781a31d0fb58257b1efb1f324a (patch) | |
| tree | ae6dbaca9ea90d3fa7ed3b16c633229a7f995dd0 /src/mem/bridge.hh | |
| parent | cc1feb9f6ddf9d0a58365ffa9f7ae948bf19901d (diff) | |
| download | gem5-780aa0a0ebb765781a31d0fb58257b1efb1f324a.tar.xz | |
Fix corner case on assertion.
I need to move over to using the fixPacket function so I don't have to make the same changes everywhere.
Still a functional access bug someplace I need to track down in timing mode.
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
Fix corner case on assertion
tests/configs/memtest.py:
Updated memtester with uncacheable addresses and functional accesses
--HG--
extra : convert_revision : e6fa851621700ff9227b83cc5cac20af4fc8444f
Diffstat (limited to 'src/mem/bridge.hh')
0 files changed, 0 insertions, 0 deletions