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authorSteve Reinhardt <stever@eecs.umich.edu>2006-05-23 17:16:45 -0400
committerSteve Reinhardt <stever@eecs.umich.edu>2006-05-23 17:16:45 -0400
commitcf826ae296a4277bdf2ce46e4484295efde5a3c2 (patch)
treebab4ed90c6c4f71b448fcf795abd6ada66c98fdb /src/mem/bus.cc
parent20051d41d50a717b6aa384e59039ca987c284932 (diff)
downloadgem5-cf826ae296a4277bdf2ce46e4484295efde5a3c2.tar.xz
Minor fixes for full-system timing memory.
Need to rewrite bus bridge to get any further. src/dev/io_device.cc: Set packet dest on timing responses. src/mem/bus.cc: Fix dest addr bounds check assertion. Add assertion to catch infinite loopbacks. src/mem/physical.cc: Add comment. --HG-- extra : convert_revision : 419b65a3a61e2d099884dbda117b338dffd80896
Diffstat (limited to 'src/mem/bus.cc')
-rw-r--r--src/mem/bus.cc3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index f7c2b874a..e8dfbc2e6 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -54,7 +54,8 @@ Bus::recvTiming(Packet *pkt)
if (pkt->dest == Packet::Broadcast) {
port = findPort(pkt->addr, pkt->src);
} else {
- assert(pkt->dest > 0 && pkt->dest < interfaces.size());
+ assert(pkt->dest >= 0 && pkt->dest < interfaces.size());
+ assert(pkt->dest != pkt->src); // catch infinite loops
port = interfaces[pkt->dest];
}
return port->sendTiming(pkt);